Parallel data paths including buses may be used to communicate binary information. In the course of data transfer across a bus, it may be desirable to determine whether the majority of bits on the bus are in a specified condition (e.g., set or reset “majority voter” status).
Some majority voter methods may employ a cascade of logic gates to count the number of bit inputs in a set condition from a small group of bit inputs (e.g. two-of-three counters), and to sum the output of the cascade. The number of gates required to implement this solution may increase geometrically with bus width. Analog majority voter methods may resistively couple bit inputs to an operational amplifier input, and couple a voltage source to the other operational amplifier input as a reference. Such solutions may consume significant static power, and using a reference voltage source may increase circuit complexity.